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INTEGRATED CIRCUITS
DATA SHEET
PCF8579 LCD column driver for dot matrix graphic displays
Product specification Supersedes data of 1996 Oct 25 File under Integrated Circuits, IC12 1997 Apr 01
Philips Semiconductors
Product specification
LCD column driver for dot matrix graphic displays
CONTENTS 1 2 3 4 5 6 7 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 7.11 7.12 8 8.1 9 9.1 9.2 9.3 9.4 FEATURES APPLICATIONS GENERAL DESCRIPTION ORDERING INFORMATION BLOCK DIAGRAM PINNING FUNCTIONAL DESCRIPTION Multiplexed LCD bias generation Power-on reset Timing generator Column drivers Display RAM Data pointer Subaddress counter I2C-bus controller Input filters RAM access Display control TEST pin I2C-BUS PROTOCOL Command decoder CHARACTERISTICS OF THE I2C-BUS Bit transfer Start and stop conditions System configuration Acknowledge 10 11 12 13 14 15 16 17 18 18.1 18.2 18.3 18.3.1 18.3.2 18.3.3 18.4 19 20 21 LIMITING VALUES HANDLING DC CHARACTERISTICS AC CHARACTERISTICS
PCF8579
APPLICATION INFORMATION CHIP DIMENSIONS AND BONDING PAD LOCATIONS CHIP-ON GLASS INFORMATION PACKAGE OUTLINES SOLDERING Introduction Reflow soldering Wave soldering LQFP VSO Method (LQFP and VSO) Repairing soldered joints DEFINITIONS LIFE SUPPORT APPLICATIONS PURCHASE OF PHILIPS I2C COMPONENTS
1997 Apr 01
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Philips Semiconductors
Product specification
LCD column driver for dot matrix graphic displays
1 FEATURES 2 APPLICATIONS
PCF8579
* LCD column driver * Used in conjunction with the PCF8578, this device forms part of a chip set capable of driving up to 40960 dots * 40 column outputs * Selectable multiplex rates; 1 : 8, 1 : 16, 1 : 24 or 1 : 32 * Externally selectable bias configuration, 5 or 6 levels * Easily cascadable for large applications (up to 32 devices) * 1280-bit RAM for display data storage * Display memory bank switching * Auto-incremented data loading across hardware subaddress boundaries (with PCF8578) * Power-on reset blanks display * Logic voltage supply range 2.5 to 6 V * Maximum LCD supply voltage 9 V * Low power consumption * I2C-bus interface * TTL/CMOS compatible * Compatible with most microcontrollers * Optimized pinning for single plane wiring in multiple device applications (with PCF8578) * Space saving 56-lead plastic mini-pack and 64-pin plastic low profile quad flat package * Compatible with chip-on-glass technology * I2C-bus address: 011110 SA0. 4 ORDERING INFORMATION TYPE NUMBER PCF8579T PCF8579U7 PCF8579H
* Automotive information systems * Telecommunication systems * Point-of-sale terminals * Computer terminals * Instrumentation. 3 GENERAL DESCRIPTION
The PCF8579 is a low power CMOS LCD column driver, designed to drive dot matrix graphic displays at multiplex rates of 1 : 8, 1 : 16, 1 : 24 or 1 : 32. The device has 40 outputs and can drive 32 x 40 dots in a 32 row multiplexed LCD. Up to 16 PCF8579s can be cascaded and up to 32 devices may be used on the same I2C-bus (using the two slave addresses). The device is optimized for use with the PCF8578 LCD row/column driver. Together these two devices form a general purpose LCD dot matrix driver chip set, capable of driving displays of up to 40960 dots. The PCF8579 is compatible with most microcontrollers and communicates via a two-line bidirectional bus (I2C-bus). To allow partial VDD shutdown the ESD protection system of the SCL and SDA pins does not use a diode connected to VDD. Communication overheads are minimized by a display RAM with auto-incremented addressing and display bank switching.
PACKAGE NAME VSO56 - LQFP64 chip with bumps on tape plastic low profile quad flat package; 64 leads; body 10 x 10 x 1.4 mm DESCRIPTION plastic very small outline package; 56 leads VERSION SOT190 - SOT314-2
1997 Apr 01
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Philips Semiconductors
Product specification
LCD column driver for dot matrix graphic displays
5 BLOCK DIAGRAM
PCF8579
C39 - C0 17 - 56 (30 to 33, 35 to 64, 1 to 6) VDD V3 V4 V LCD 12 (20) 14 (22) 15 (23) 16 (24) COLUMN DRIVERS (1)
PCF8579
TEST VSS
6 (12) 5 (11)
OUTPUT CONTROLLER
Y DECODER AND SENSING AMPLIFIERS
32 x 40 BIT DISPLAY RAM
DISPLAY DECODER
POWER-ON RESET
X DECODER
A3 A2 A1 A0
8 (14) 9 (16) 10 (17) 11 (18)
(9) 3 SUBADDRESS COUNTER RAM DATA POINTER Y X TIMING GENERATOR SYNC (10) 4 CLK
SCL SDA
2 (8) 1 (7) INPUT FILTERS (15, 19, 21, 25 to 29, 34) 13 n.c.
I 2 C-BUS CONTROLLER
COMMAND DECODER
7 (13)
MSA919
SA0
(1) Operates at LCD voltage levels, all other blocks operate at logic levels. The pin numbers given in parenthesis refer to the LQFP64 package.
Fig.1 Block diagram.
1997 Apr 01
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Philips Semiconductors
Product specification
LCD column driver for dot matrix graphic displays
6 PINNING PINS SYMBOL VSO56 SDA SCL SYNC CLK VSS TEST SA0 A3 to A0 VDD n.c. V3, V4 VLCD C39 to C0 Note 1. Do not connect, this pin is reserved. 1 2 3 4 5 6 7 8 to 11 12 13(1) 14 and 15 16 17 to 56 LQFP64 7 8 9 10 11 12 13 14, 16 to 18 20 15, 19, 21,25 to 29, 34 22 and 23 24 30 to 33, 35 to 64 and 1 to 6
PCF8579
DESCRIPTION I2C-bus serial data input/output I2C-bus serial clock input cascade synchronization input external clock input ground (logic) test pin (connect to VSS) I2C-bus slave address input (bit 0) I2C-bus subaddress inputs supply voltage not connected LCD bias voltage inputs LCD supply voltage LCD column driver outputs
1997 Apr 01
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Philips Semiconductors
Product specification
LCD column driver for dot matrix graphic displays
PCF8579
SDA SCL SYNC CLK V SS TEST SA0 A3 A2
1 2 3 4 5 6 7 8 9
56
C0
55 C1 54 53 52 51 50 49 48 47 46 C2 C3 C4 C5 C6 C7 C8 C9 C10
A1 10 A0 11 V DD 12 n.c. 13 V 3 14
45 C11 44 C12 43 C13
PCF8579
V 4 15 V LCD 16 C39 17 C38 18 C37 C36 C35 C34 C33 C32 C31 C30 C29 C28 19 20 21 22 23 24 25 26 27 28
MSA918
42 C14 41 C15 40 C16 39 C17 38 C18 37 C19 36 C20 35 C21 34 C22 33 C23 32 C24 31 C25 30 C26 29 C27
Fig.2 Pin configuration (VSO56).
1997 Apr 01
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Philips Semiconductors
Product specification
LCD column driver for dot matrix graphic displays
PCF8579
60 C10
59 C11
58 C12
57 C13
56 C14
55 C15
54 C16
53 C17
52 C18
51 C19
50 C20
64 C6
63 C7
62 C8
61 C9
handbook, full pagewidth
49 C21 48 C22 47 C23 46 C24 45 C25 44 C26 43 C27 42 C28 41 C29 40 C30 39 C31 38 C32 37 C33 36 C34 35 C35 34 n.c. 33 C36 C37 32
MBH590
C5 1 C4 2 C3 3 C2 4 C1 5 C0 6 SDA 7 SCL 8
PCF8579
SYNC 9 CLK 10 VSS 11 TEST 12 SA0 13 A3 14 n.c. 15 A2 16 A1 17 A0 18 n.c. 19 VDD 20 n.c. 21 V3 22 V4 23 VLCD 24 n.c. 25 n.c. 26 n.c. 27 n.c. 28 n.c. 29 C39 30 C38 31
Fig.3 Pin configuration (LQFP64).
1997 Apr 01
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Philips Semiconductors
Product specification
LCD column driver for dot matrix graphic displays
7 FUNCTIONAL DESCRIPTION
PCF8579
The PCF8579 column driver is designed for use with the PCF8578. Together they form a general purpose LCD dot matrix chip set. Typically up to 16 PCF8579s may be used with one PCF8578. Each of the PCF8579s is identified by a unique 4-bit hardware subaddress, set by pins A0 to A3. The PCF8578 can operate with up to 32 PCF8579s when using two I2C-bus slave addresses. The two slave addresses are set by the logic level on input SA0. 7.1 Multiplexed LCD bias generation
1.0 V bias Vop 0.8 V3 0.6 V2
MSA838
0.4 V4 0.2 V5 0
The bias levels required to produce maximum contrast depend on the multiplex rate and the LCD threshold voltage (Vth). Vth is typically defined as the RMS voltage at which the LCD exhibits 10% contrast. Table 1 shows the optimum voltage bias levels for the PCF8578/PCF8579 chip set as functions of Vop (Vop = VDD - VLCD), together with the discrimination ratios (D) for the different multiplex rates. A practical value for Vop is obtained by equating Voff(rms) with Vth. Figure 4 shows the first 4 rows of Table 1 as graphs. Table 1 Optimum LCD bias voltages MULTIPLEX RATE PARAMETER 1:8 V2 -------V op V3 -------V op V4 -------V op V5 -------V op V off ( rms ) ---------------------V op V on ( rms ) ---------------------V op V on ( rms ) D = ---------------------V off ( rms ) V op -------V th 1997 Apr 01 0.739 1 : 16 0.800 1 : 24 0.830 1 : 32 0.850 7.2
1:8
1:16
1:24 1:32 multiplex rate
Vbias = V2, V3, V4, V5. See Table 1.
Fig.4
Vbias/Vop as a function of the multiplex rate.
Power-on reset
At power-on the PCF8579 resets to a defined starting condition as follows: 1. Display blank (in conjunction with PCF8578) 2. 1 : 32 multiplex rate 3. Start bank, 0 selected 4. Data pointer is set to X, Y address 0, 0 5. Character mode 6. Subaddress counter is set to 0 7. I2C-bus is initialized. Data transfers on the I2C-bus should be avoided for 1 ms following power-on, to allow completion of the reset action.
0.522
0.600
0.661
0.700
0.478
0.400
0.339
0.300
0.261
0.200
0.170
0.150
0.297
0.245
0.214
0.193
0.430
0.316
0.263
0.230
1.447
1.291
1.230
1.196
3.370
4.080
4.680
5.190
8
Philips Semiconductors
Product specification
LCD column driver for dot matrix graphic displays
PCF8579
T frame 0 VDD V2 V3 V4 V5 V LCD VDD V2 V3 V4 V5 V LCD SYNC 0 VDD V2 V3 V4 V5 V LCD VDD V2 V3 V4 V5 V LCD SYNC 0 VDD V2 V3 V4 V5 V LCD VDD V2 V3 V4 V5 V LCD SYNC 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 VDD V2 V3 V4 V5 V LCD VDD V2 V3 V4 V5 V LCD SYNC
MSA841
ON 4 5 6 7 OFF
1
2
3
ROW 0
1:8
COLUMN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
ROW 0
1:16
COLUMN
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
ROW 0
1:24
COLUMN
ROW 0
1:32
COLUMN
column display
Fig.5 LCD row/column waveforms.
1997 Apr 01
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Philips Semiconductors
Product specification
LCD column driver for dot matrix graphic displays
PCF8579
T frame VDD V2 V3 V4 V5 V LCD VDD V2 V3 V4 V5 V LCD VDD V2 V3 V4 V5 V LCD VDD V2 V3 V4 V5 V LCD V op 0.261 Vop V state 1 (t) 0V 0.261 Vop
state 1 (OFF) state 2 (ON)
ROW 1 R1 (t)
ROW 2 R2 (t)
dot matrix 1:8 multiplex rate
COL 1 C1 (t)
COL 2 C2 (t)
V op V op 0.478 Vop 0.261 Vop V state 2 (t) 0V 0.261 Vop 0.478 Vop V op
MSA840
V state 1 (t) = C1(t)
R1(t): 8 8( 8 1 1) = 0.430
general relationship (n = multiplex rate)
Von(rms) V op
=
1 8
Von(rms) V op
=
1 n
n1 n ( n 1)
V state 2 (t) = C2(t)
R2(t):
Voff(rms) V op
=
2 ( 8 1) = 0.297 8 ( 8 1) 2
Voff(rms) = V op
2 ( n 1) n ( n 1) 2
Fig.6 LCD drive mode waveforms for 1 : 8 multiplex rate.
1997 Apr 01
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Philips Semiconductors
Product specification
LCD column driver for dot matrix graphic displays
PCF8579
T frame VDD V2 V3 V4 V5 V LCD VDD V2 V3 V4 V5 V LCD VDD V2 V3 V4 V5 V LCD VDD V2 V3 V4 V5 V LCD V op
state 1 (OFF) state 2 (ON)
ROW 1 R1 (t)
ROW 2 R2 (t)
COL 1 C1 (t)
dot matrix 1:16 multiplex rate
COL 2 C2 (t)
0.2 Vop V state 1 (t) 0V 0.2 Vop
V op V op 0.6 Vop V state 2 (t) 0.2 Vop 0V 0.2 Vop 0.6 Vop V op
MSA836
V state 1 (t) = C1(t)
R1(t):
general relationship (n = multiplex rate)
Von(rms) V op
=
1 16 1 = 0.316 16 16 ( 16 1 ) R2(t):
Von(rms) V op
=
1 n
n1 n ( n 1)
V state 2 (t) = C2(t)
V off(rms) V op
=
2 ( 16 1) = 0.254 16 ( 16 1 ) 2
Voff(rms) = V op
2 ( n 1) n ( n 1) 2
Fig.7 LCD drive mode waveforms for 1 : 16 multiplex rate.sa.
1997 Apr 01
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Philips Semiconductors
Product specification
LCD column driver for dot matrix graphic displays
7.3 Timing generator 7.10 RAM access
PCF8579
The timing generator of the PCF8579 organizes the internal data flow from the RAM to the display drivers. An external synchronization pulse SYNC is received from the PCF8578. This signal maintains the correct timing relationship between cascaded devices. 7.4 Column drivers
There are three RAM ACCESS modes: * Character * Half-graphic * Full-graphic. These modes are specified by bits G1 and G0 of the RAM ACCESS command. The RAM ACCESS command controls the order in which data is written to or read from the RAM (see Fig.8). To store RAM data, the user specifies the location into which the first byte will be loaded (see Fig.9): * Device subaddress (specified by the DEVICE SELECT command) * RAM X-address (specified by the LOAD X-ADDRESS command) * RAM bank (specified by bits Y1 and Y0 of the RAM ACCESS command). Subsequent data bytes will be written or read according to the chosen RAM access mode. Device subaddresses are automatically incremented between devices until the last device is reached. If the last device has subaddress 15, further display data transfers will lead to a wrap-around of the subaddress to 0. 7.11 Display control
Outputs C0 to C39 are column drivers which must be connected to the LCD. Unused outputs should be left open-circuit. 7.5 Display RAM
The PCF8579 contains a 32 x 40-bit static RAM which stores the display data. The RAM is divided into 4 banks of 40 bytes (4 x 8 x 40 bits). During RAM access, data is transferred to/from the RAM via the I2C-bus. 7.6 Data pointer
The addressing mechanism for the display RAM is realized using the data pointer. This allows an individual data byte or a series of data bytes to be written into, or read from, the display RAM, controlled by commands sent on the I2C-bus. 7.7 Subaddress counter
The storage and retrieval of display data is dependent on the content of the subaddress counter. Storage and retrieval take place only when the contents of the subaddress counter agree with the hardware subaddress at pins A0, A1, A2 and A3. 7.8 I2C-bus controller
The display is generated by continuously shifting rows of RAM data to the dot matrix LCD via the column outputs. The number of rows scanned depends on the multiplex rate set by bits M1 and M0 of the SET MODE command. The display status (all dots on/off and normal/inverse video) is set by bits E1 and E0 of the SET MODE command. For bank switching, the RAM bank corresponding to the top of the display is set by bits B1 and B0 of the SET START BANK command. This is shown in Fig.10 This feature is useful when scrolling in alphanumeric applications. 7.12 TEST pin
The I2C-bus controller detects the I2C-bus protocol, slave address, commands and display data bytes. It performs the conversion of the data input (serial-to-parallel) and the data output (parallel-to-serial). The PCF8579 acts as an I2C-bus slave transmitter/receiver. Device selection depends on the I2C-bus slave address, the hardware subaddress and the commands transmitted. 7.9 Input filters
The TEST pin must be connected to VSS. To enhance noise immunity in electrically adverse environments, RC low-pass filters are provided on the SDA and SCL lines.
1997 Apr 01
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RAM 4 bytes 1 byte 0 1 2 3
Philips Semiconductors
LCD column driver for dot matrix graphic displays
PCF8579
driver 1
PCF8579
driver 2
PCF8579
driver k
bank 0 bank 1 bank 2 bank 3 PCF8579 system RAM 1 k 16 LSB
40-bits
4
5
6
7
8
9 10 11 character mode MSB
13
0 2 bytes 1 3 5 7 9 11 13 15 17 19 21 23 half-graphic mode 2 4 6 8 10 12 14 16 18 20 22 0 1 4 bytes 2 3 6 10 14 18 22 26 30 34 38 42 46 7 11 15 19 23 27 31 35 39 43 47 RAM data bytes are written or read as indicated above full-graphic mode
MSA921
4 5
8 12 16 20 24 28 32 36 40 44 9 13 17 21 25 29 33 37 41 45
Product specification
PCF8579
Fig.8 RAM access mode.
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DEVICE SELECT: subaddress 12 RAM ACCESS: character mode bank 1 RAM bank 0 bank 1 bank 2 bank 3 LOAD X-ADDRESS: X-address = 8 R/ W slave address READ S
Philips Semiconductors
LCD column driver for dot matrix graphic displays
S 011110A1A
0
DATA
A
14
slave address
R/W DEVICE SELECT LOAD X-ADDRESS RAM ACCESS
S
S 011110A0A11101100A10001000A01110001A 0
last command
WRITE
DATA
A
DATA
A
MSA835
Product specification
PCF8579
Fig.9 Example of commands specifying initial data byte RAM locations.
Philips Semiconductors
Product specification
LCD column driver for dot matrix graphic displays
PCF8579
RAM
bank 0 top of LCD
bank 1
LCD
bank 2
bank 3
MSA851
Fig.10 Relationship between display and SET START BANK; 1 : 32 multiplex rate and start bank = 2.
1997 Apr 01
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Philips Semiconductors
Product specification
LCD column driver for dot matrix graphic displays
8 I2C-BUS PROTOCOL
PCF8579
Two 7-bit slave addresses (0111100 and 0111101) are reserved for both the PCF8578 and PCF8579. The least significant bit of the slave address is set by connecting input SA0 to either logic 0 (VSS) or logic 1 (VDD). Therefore, two types of PCF8578 or PCF8579 can be distinguished on the same I2C-bus which allows: 1. One PCF8578 to operate with up to 32 PCF8579s on the same I2C-bus for very large applications. 2. The use of two types of LCD multiplex schemes on the same I2C-bus. In most applications the PCF8578 will have the same slave address as the PCF8579. The I2C-bus protocol is shown in Fig.11. All communications are initiated with a start condition (S) from the I2C-bus master, which is followed by the desired slave address and read/write bit. All devices with this slave address acknowledge in parallel. All other devices ignore the bus transfer. In WRITE mode (indicated by setting the read/write bit LOW) one or more commands follow the slave address acknowlegement. The commands are also acknowledged by all addressed devices on the bus. The last command must clear the continuation bit C. After the last command a series of data bytes may follow. The acknowlegement after each byte is made only by the (A0, A1, A2 and A3) addressed PCF8579 or PCF8578 with its implicit subaddress 0. After the last data byte has been acknowledged, the I2C-bus master issues a stop condition (P).
In READ mode, indicated by setting the read/write bit HIGH, data bytes may be read from the RAM following the slave address acknowlegement. After this acknowlegement the master transmitter becomes a master receiver and the PCF8579 becomes a slave transmitter. The master receiver must acknowledge the reception of each byte in turn. The master receiver must signal an end of data to the slave transmitter, by not generating an acknowledge on the last byte clocked out of the slave. The slave transmitter then leaves the data line HIGH, enabling the master to generate a stop condition (P). Display bytes are written into, or read from, the RAM at the address specified by the data pointer and subaddress counter. Both the data pointer and subaddress counter are automatically incremented, enabling a stream of data to be transferred either to, or from, the intended devices. In multiple device applications, the hardware subaddress pins of the PCF8579s (A0 to A3) are connected to VSS or VDD to represent the desired hardware subaddress code. If two or more devices share the same slave address, then each device must be allocated a unique hardware subaddress.
1997 Apr 01
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Philips Semiconductors
Product specification
LCD column driver for dot matrix graphic displays
PCF8579
R/ W slave address S
acknowledge by all addressed PCF8578s / PCF8579s
acknowledge by A0, A1, A2 and A3 selected PCF8578s / PCF8579s only
S 0 1 1 1 1 0A 0AC
0 1 byte n
COMMAND
A
DISPLAY DATA
A
P
0 byte(s)
n
0 byte(s) update data pointers and if necessary, subaddress counter
(a)
MSA830
acknowledge by all addressed PCF8578s / PCF8579s slave address S 0 1 1 1 1 0A0 AC 0 slave address S COMMAND A acknowledge from master no acknowledge from master
S
S 011110A1A
0
DATA
A
DATA
1
P
n R/ W
1 byte R/W at this moment master transmitter becomes a master receiver and PCF8578/PCF8579 slave receiver becomes a slave transmitter
n bytes
last byte
update data pointers and if necessary subaddress counter
MSA832
(b)
acknowledge by all addressed PCF8578s / PCF8579s slave address S
acknowledge from master
no acknowledge from master
S 011110A1A
0
MSA831
DATA
A
DATA
1
P
R/ W
n bytes
last byte update data pointers and if necessary, subaddress counter
(c)
Fig.11 (a) Master transmits to slave receiver (WRITE mode); (b) Master reads after sending command string (WRITE commands; READ data); (c) Master reads slave immediately after sending slave address (READ mode).
1997 Apr 01
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Philips Semiconductors
Product specification
LCD column driver for dot matrix graphic displays
8.1 Command decoder
MSB C REST OF OPCODE
PCF8579
The command decoder identifies command bytes that arrive on the I2C-bus. The most significant bit of a command is the continuation bit C (see Fig.12). When this bit is set, it indicates that the next byte to be transferred will also be a command. If the bit is reset, it indicates the conclusion of the command transfer. Further bytes will be regarded as display data. Commands are transferred in WRITE mode only. The five commands available to the PCF8579 are defined in Tables 2 and 3. Table 2 Summary of commands COMMAND SET MODE SET START BANK DEVICE SELECT RAM ACCESS LOAD X-ADDRESS Note 1. C = command continuation bit. D = may be a logic 1 or 0. C C C C C 1 1 1 1 0 0 1 1 1 D OPCODE(1) D 1 0 1 D D 1 D D D D 1 D D D D D D D D D D D D D
LSB
MSA833
C = 0; last command. C = 1; commands continue.
Fig.12 General format of command byte.
DESCRIPTION multiplex rate, display status, system type defines bank at top of LCD defines device subaddress graphic mode, bank select (D D D D 12 is not allowed; see SET START BANK opcode) 0 to 39
1997 Apr 01
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Philips Semiconductors
Product specification
LCD column driver for dot matrix graphic displays
Table 3 Definition of PCF8578/PCF8579 commands COMMAND SET MODE C 1 0 OPCODE T OPTIONS see Table 5 see Table 6 SET START BANK C 1 1 1 1 1 B1 B0 see Table 7
PCF8579
DESCRIPTION defines LCD drive mode defines display status defines system type defines pointer to RAM bank corresponding to the top of the LCD; useful for scrolling, pseudo motion and background preparation of new display four bits of immediate data, bits A0 to A3, are transferred to the subaddress counter to define one of sixteen hardware subaddresses defines the auto-increment behaviour of the address for RAM access
E1 E0 M1 M0 see Table 4
DEVICE SELECT
C
1
1
0
A3 A2 A1 A0 see Table 8
RAM ACCESS
C
1
1
1
G1 G0 Y1 Y0 see Table 9
see Table 10 two bits of immediate data, bits Y0 to Y1, are transferred to the X-address pointer to define one of forty display RAM columns LOAD X-ADDRESS C 0 X5 X4 X3 X2 X1 X0 see Table 11 six bits of immediate data, bits X0 to X5, are transferred to the X-address pointer to define one of forty display RAM columns
1997 Apr 01
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Philips Semiconductors
Product specification
LCD column driver for dot matrix graphic displays
Table 4 Set mode option 1 BITS LCD DRIVE MODE M1 1:8 1 : 16 1 : 24 1 : 32 MUX ( 8 rows) MUX (16 rows) MUX (24 rows) MUX (32 rows) 0 1 1 0 M0 1 0 1 0 Character Table 5 Set mode option 2 BITS DISPLAY STATUS E1 Blank Normal All segments on Inverse video Table 6 Set mode option 3 SYSTEM TYPE PCF8578 row only PCF8578 mixed mode Table 7 Set start bank option 1 BITS START BANK POINTER B1 Bank 0 Bank 1 Bank 2 Bank 3 0 0 1 1 B0 0 1 0 1 BIT T 0 1 Table 11 Load X-address option 1 DESCRIPTION Decimal value of 0 to 39 0 0 1 1 E0 0 1 0 1 Table 10 RAM access option 2 DESCRIPTION Decimal value of 0 to 3 Y1 Half-graphic Full-graphic Not allowed (note 1) Note Table 8 Device select option 1 DESCRIPTION Decimal value of 0 to 15 Table 9 RAM access option 1 A3
PCF8579
BITS A2 A1 A0
BITS RAM ACCESS MODE G1 0 0 1 1 G0 0 1 0 1
1. See opcode for SET START BANK in Table 3.
BITS Y0
BITS X5 X4 X3 X2 X1 X0
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Philips Semiconductors
Product specification
LCD column driver for dot matrix graphic displays
9 CHARACTERISTICS OF THE I2C-BUS 9.4 Acknowledge
PCF8579
The I2C-bus is for bidirectional, two-line communication between different ICs or modules. The two lines are a serial data line (SDA) and a serial clock line (SCL) which must be connected to a positive supply via a pull-up resistor. Data transfer may be initiated only when the bus is not busy. 9.1 Bit transfer
One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse as changes in the data line at this moment will be interpreted as control signals. 9.2 Start and stop conditions
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line, while the clock is HIGH, is defined as the start condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH, is defined as the stop condition (P). 9.3 System configuration
The number of data bytes transferred between the start and stop conditions from transmitter to receiver is unlimited. Each data byte of eight bits is followed by one acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter, whereas the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges must pull down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse (set-up and hold times must be taken into consideration). A master receiver must signal the end of a data transmission to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event the transmitter must leave the data line HIGH to enable the master to generate a stop condition.
A device transmitting a message is a `transmitter', a device receiving a message is the `receiver'. The device that controls the message flow is the `master' and the devices which are controlled by the master are the `slaves'.
SDA
SCL data line stable; data valid change of data allowed
MBA607
Fig.13 Bit transfer.
1997 Apr 01
21
Philips Semiconductors
Product specification
LCD column driver for dot matrix graphic displays
PCF8579
SDA
SDA
SCL S START condition P STOP condition
SCL
MBA608
Fig.14 Definition of start and stop condition.
SDA SCL MASTER TRANSMITTER / RECEIVER SLAVE TRANSMITTER / RECEIVER MASTER TRANSMITTER / RECEIVER
MBA605
SLAVE RECEIVER
MASTER TRANSMITTER
Fig.15 System configuration.
handbook, full pagewidth
START condition SCL FROM MASTER 1 2 8
clock pulse for acknowledgement 9
DATA OUTPUT BY TRANSMITTER S DATA OUTPUT BY RECEIVER
MBA606 - 1
The general characteristics and detailed specification of the I2C-bus are available on request.
Fig.16 Acknowledgement on the I2C-bus.
1997 Apr 01
22
Philips Semiconductors
Product specification
LCD column driver for dot matrix graphic displays
10 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL VDD VLCD Vi1 Vi2 Vo1 Vo2 II IO Ptot Po Tstg supply voltage LCD supply voltage input voltage pins SDA, SCL, SYNC, CLK, TEST, SA0, A0, A1, A2 and A3 input voltage pins V3 and V4 output voltage pin SDA output voltage pins C0 to C39 DC input current DC output current total power dissipation per package power dissipation per output storage temperature PARAMETER MIN. -0.5 VDD - 11 VSS - 0.5 VLCD - 0.5 VSS - 0.5 VLCD - 0.5 -10 -10 -50 - - -65 MAX. +8.0 VDD VDD + 0.5 VDD + 0.5 VDD + 0.5 VDD + 0.5 +10 +10 +50 400 100 +150
PCF8579
UNIT V V V V V V mA mA mA mW mW C
IDD, ISS, ILCD current at pins VDD, VSS or VLCD
11 HANDLING Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe it is desirable to take normal precautions appropriate to handling MOS devices. Advice can be found in Data Handbook IC12 under "Handling MOS Devices".
1997 Apr 01
23
Philips Semiconductors
Product specification
LCD column driver for dot matrix graphic displays
PCF8579
12 DC CHARACTERISTICS VDD = 2.5 to 6 V; VSS = 0 V; VLCD = VDD - 3.5 V to VDD - 9 V; Tamb = -40 to +85 C; unless otherwise specified. SYMBOL Supplies VDD VLCD IDD VPOR Logic VIL VIH ILI1 LOW level input voltage HIGH level input voltage leakage current at pins SDA, SCL, SYNC, CLK, TEST, SA0, A0, A1, A2 and A3 LOW level output current at pin SDA input capacitance Vi = VDD or VSS VSS 0.7VDD -1 - - - 0.3VDD VDD +1 V V A supply voltage LCD supply voltage supply current power-on reset level fCLK = 2 kHz; note 1 note 2 2.5 VDD - 9 - - - - 9 1.3 6.0 20 1.8 V A V VDD - 3.5 V PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
IOL Ci ILI2 VDC RCOL Notes
VOL = 0.4 V; VDD = 5 V 3 note 3 - -2 - note 4 -
- - - 20 3
- 5
mA pF A mV k
LCD outputs leakage current at pins V3 to V4 DC component of LCD drivers pins C0 to C39 output resistance at pins C0 to C39 Vi = VDD or VLCD +2 - 6
1. Outputs are open; inputs at VDD or VSS; I2C-bus inactive; clock with 50% duty factor. 2. Resets all logic when VDD < VPOR. 3. Periodically sampled; not 100% tested. 4. Resistance measured between output terminal (C0 to C39) and bias input (V3, V4, VDD and VLCD) when the specified current flows through one output under the following conditions (see Table 1): a) - Vop = VDD - VLCD = 9 V; b) - V3 - VLCD 4.70 V; V4 - VLCD 4.30 V; ILOAD = 100 A.
1997 Apr 01
24
Philips Semiconductors
Product specification
LCD column driver for dot matrix graphic displays
PCF8579
13 AC CHARACTERISTICS All timing values are referred to VIH and VIL levels with an input voltage swing of VSS to VDD. VDD = 2.5 to 6 V; VSS = 0 V; VLCD = VDD - 3.5 V to VDD - 9 V; Tamb = -40 to +85 C; unless otherwise specified. SYMBOL fclk tPLCD I2C-bus fSCL tSW tBUF tSU;STA tHD;STA tLOW tHIGH tr tf tSU;DAT tHD;DAT tSU;STO Note 1. Typically 0.9 to 3.3 kHz. SCL clock frequency tolerable spike width on bus bus free time START condition set-up time START condition hold time SCL LOW time SCL HIGH time SCL and SDA rise time SCL and SDA fall time data set-up time data hold time STOP condition set-up time repeated start codes only - - 4.7 4.7 4.0 4.7 4.0 - - 250 0 4.0 - - - - - - - - - - - - 100 100 - - - - - 1.0 0.3 - - - kHz ns s s s s s s s ns ns s PARAMETER clock frequency driver delays CONDITIONS 50% duty factor VDD - VLCD = 9 V; with test loads - - MIN. - TYP. note 1 MAX. 10 100 UNIT kHz s
SDA
1.5 k (2%)
VDD
C0 to C39
1 nF
MSA916
Fig.17 AC test loads.
1997 Apr 01
25
Philips Semiconductors
Product specification
LCD column driver for dot matrix graphic displays
PCF8579
1/ f CLK 0.7 VDD 0.3 V DD
CLK
0.5 V C0 to C39 (V DD V LCD = 9 V) 0.5 V t PLCD
MSA917
Fig.18 Driver timing waveforms.
k, full pagewidth
SDA
t BUF
t LOW
tf
SCL
t
HD;STA
tr
t HD;DAT
t HIGH
t SU;DAT
SDA t SU;STA
MGA728
t
SU;STO
Fig.19 I2C-bus timing waveforms.
1997 Apr 01
26
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V DD V DD C C C C C R V2 R V3 (4 2 3)R V4 R V5 R VLCD VLCD VSS VSS OSC R OSC VSS V DD PCF8578 (ROW MODE) 8 unused columns 40 columns subaddress 0 40 columns subaddress 1 40 columns subaddress k 1 32 rows
14 APPLICATION INFORMATION
Philips Semiconductors
LCD column driver for dot matrix graphic displays
LCD DISPLAY
1:32 multiplex rate 32 x 40 x k dots (k (20480 dots max.)
16)
SA0
VSS
V DD
V DD VLCD V3 1 PCF8579
A0 A1 A2
V DD
V DD VLCD V3 2 PCF8579
A0 A1 A2
V DD
V DD VLCD V3 V4 k PCF8579
A0 A1 A2 A3
SDA SCL CLK SYNC
A3 V4 VSS SYNC CLK SCL SDA SA0 VSS VSS
A3 V4 VSS SYNC CLK SCL SDA SA0 VSS VSS
27
SCL SDA
VSS SYNC CLK SCL SDA SA0 VSS VSS
MSA845
Product specification
PCF8579
Fig.20 Typical LCD driver system with 1 : 32 multiplex rate.
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V DD VSS V DD VSS V DD VSS SA0 SDA SCL CLK SYNC VSS A3 V3 A2 k V4 PCF8579 A1 V LCD A0 40 columns V DD V DD subaddress 1 SA0 SDA SCL CLK SYNC VSS A3 V3 A2 V4 2 PCF8579 A1 VLCD A0 40 columns 1:16 multiplex rate 16 x 40 x k dots (k (10240 dots max.) 1:16 multiplex rate 16 x 40 x k dots (k (10240 dots max.) 40 columns V DD V DD subaddress 0 SA0 SDA SCL CLK SYNC VSS A3 V3 A2 A1 A0 40 columns 1 PCF8579 V4 VLCD V DD V DD subaddress k 1 V DD 16 V DD C C C C C R V2 R V3 R V4 R V5 R V LCD VLCD VSS VSS OSC R OSC VSS V DD PCF8578 (ROW MODE) 8 unused columns V DD VSS / V DD V DD VLCD V3 V4 1 PCF8579 rows rows 16
Philips Semiconductors
LCD column driver for dot matrix graphic displays
LCD DISPLAY
16)
28
SCL SDA
16)
subaddress 0
40 columns
subaddress 1
40 columns
subaddress k 1
SA0
A0 A1 A2 A3
V DD
V DD VLCD V3 2 PCF8579
A0 A1 A2
V DD
V DD VLCD V3 k PCF8579
A0 A1 A2
SDA SCL CLK SYNC
VSS SYNC CLK SCL SDA SA0 VSS VSS
V4 A3 VSS SYNC CLK SCL SDA SA0 VSS VSS
V4 A3 VSS SYNC CLK SCL SDA SA0 VSS VSS
MSA847
Product specification
PCF8579
Fig.21 Split screen application with 1 : 16 multiplex rate for improved contrast.
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V DD VSS V DD VSS V DD VSS SA0 SDA SCL CLK SYNC VSS A3 V3 A2 k V4 PCF8579 A1 V LCD A0 40 columns V DD V DD subaddress 1 SA0 SDA SCL CLK SYNC VSS A3 V3 A2 V4 2 PCF8579 A1 VLCD A0 40 columns 1:32 multiplex rate 32 x 40 x k dots (k (20480 dots max.) 1:32 multiplex rate 32 x 40 x k dots (k (20480 dots max.) 40 columns V DD V DD subaddress 0 SA0 SDA SCL CLK SYNC VSS A3 V3 A2 V4 1 PCF8579 A1 VLCD A0 40 columns V DD V DD subaddress k 1 V DD V DD C R V2 R (4 2 3)R V3 C V4 C C R V5 R V LCD VLCD VSS VSS OSC R OSC VSS V DD PCF8578 (ROW MODE) 8 unused columns V DD VSS / V DD V DD VLCD V3 V4 1 PCF8579 32 rows
Philips Semiconductors
LCD column driver for dot matrix graphic displays
LCD DISPLAY
16) 32 16)
29
SCL SDA
C
subaddress 0
40 columns
subaddress 1
40 columns
subaddress k 1
SA0
A0 A1 A2 A3
V DD
V DD VLCD V3 2 PCF8579
A0 A1 A2
V DD
V DD VLCD V3 k PCF8579
A0 A1 A2
SDA SCL CLK SYNC
VSS SYNC CLK SCL SDA SA0 VSS VSS
V4 A3 VSS SYNC CLK SCL SDA SA0 VSS VSS
V4 A3 VSS SYNC CLK SCL SDA SA0 VSS VSS
MSA846
Product specification
PCF8579
Fig.22 Split screen application with 1 : 32 multiplex rate.
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(4 2 3)R R R R OSC R R n.c. n.c.
Philips Semiconductors
LCD column driver for dot matrix graphic displays
VSS SCL SDA V DD V LCD R0
LCD DISPLAY
PCF8578
R31/C31
30
C0
C27
C28
C39
C0
C27
C28
C39
PCF8579
PCF8579
Fig.23 Example of single plane wiring, single screen with 1 : 32 multiplex rate (PCF8578 in row driver mode).
n. c.
n. c.
to other PCF8579s
Product specification
MSA852
PCF8579
Philips Semiconductors
Product specification
LCD column driver for dot matrix graphic displays
15 CHIP DIMENSIONS AND BONDING PAD LOCATIONS
PCF8579
y SYNC TEST SDA VSS CLK SCL SA0 C0 C1 C2 C3 53 A3 C4
52 51 50 49 48 47 46
8
7
6
5
4
3
2
1
56
55
54
A2 A1 A0
9 10 11
C5 C6 C7 C8 C9 C10 C11 C12 C13 x C14 C15 C16 C17 C18 C19 C20 C21 C22
VDD n.c. V3 4.76 mm V4 VLCD
12 13 14 15 16 45 44
0 0
43 42 41 40 39 38
PCF8579
C39 C38 C37 C36
17 18 19 20
37 36 35 34
21
22
23
24
25
26
27
28
29
30
31
32
33
C31
C30
C29
C28
C27
C25
C24
C35
C33
C34
C32
3.02 mm
C26
C23
MSA920
Chip area: 14.37 mm2. Bonding pad dimensions: 120 m x 120 m. Gold bump dimensions (if ordered): 94 x 94 x 25 m. The numbers given in the square boxes refer to the pad number.
Fig.24 Bonding pad locations.
1997 Apr 01
31
Philips Semiconductors
Product specification
LCD column driver for dot matrix graphic displays
Table 12 Bonding pad locations (dimensions in m) All x/y coordinates are referenced to centre of chip, see Fig.24. PINS PAD NUMBER 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 SYMBOL SDA SCL SYNC CLK VSS TEST SA0 A3 A2 A1 A0 VDD n.c. V3 V4 VLCD C39 C38 C37 C36 C35 C34 C33 C32 C31 C30 C29 C28 C27 C26 C25 C24 C23 C22 C21 C20 C19 x 252 48 -156 -360 -564 -786 -1032 -1314 -1314 -1314 -1314 -1314 -1314 -1314 -1314 -1314 -1314 -1314 -1314 -1314 -1314 -1032 -786 -564 -360 -156 48 252 498 702 906 1110 1314 1314 1314 1314 1314 y VSO56 2142 2142 2142 2142 2142 2142 2142 2142 1920 1716 1512 708 504 300 96 -108 -1308 -1512 -1716 -1920 -2142 -2142 -2142 -2142 -2142 -2142 -2142 -2142 -2142 -2142 -2142 -2142 -2142 -1830 -1570 -1326 -1122 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37
PCF8579
LQFP64 7 8 9 10 11 12 13 14 16 17 18 20 21 22 23 24 30 31 32 33 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51
1997 Apr 01
32
Philips Semiconductors
Product specification
LCD column driver for dot matrix graphic displays
PINS PAD NUMBER 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 - SYMBOL C18 C17 C16 C15 C14 C13 C12 C11 C10 C9 C8 C7 C6 C5 C4 C3 C2 C1 C0 n.c. x 1314 1314 1314 1314 1314 1314 1314 1314 1314 1314 1314 1314 1314 1314 1314 1110 906 702 498 - y VSO56 -918 -714 -510 -306 -102 102 306 510 714 918 1122 1326 1566 1830 2142 2142 2142 2142 2142 - 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 -
PCF8579
LQFP64 52 53 54 55 56 57 58 59 60 61 62 63 64 1 2 3 4 5 6 15, 19, 21, 25 to 29, 34
1997 Apr 01
33
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PCF8578 PCF8579
R0 to R31 C0 C1 C2
16 CHIP-ON GLASS INFORMATION
Philips Semiconductors
VDD V3 V4 VLCD VSS CLK SYNC SCL SDA
VDD
LCD column driver for dot matrix graphic displays
SC
R O
SA TE ST
0 O SC
D
V D
A3 A2 A1
VS S C LK C SY N SC L SD A R 0 R 1 R 2
V V2 3
V 4
A0
V3 V4 VLCD
SA 0 TE
V V5 LC D
ST D V D
VS S C LK C SY N SC L SD A C 0 C 1
VSS
c.
n.
CLK SYNC SCL SDA
C
39
C
38
V V4 LC D C 39 C C 37 38
V 3
Product specification
LCD DISPLAY
PCF8579
MSA850
If inputs SA0 and A0 to A3 are left unconnected they are internally pulled-up to VDD.
Fig.25 Typical chip-on glass application (viewed from underside of chip).
Philips Semiconductors
Product specification
LCD column driver for dot matrix graphic displays
17 PACKAGE OUTLINES VSO56: plastic very small outline package; 56 leads
PCF8579
SOT190-1
D
E
A X
c y HE vM A
Z 56 29
Q A2 A1 pin 1 index Lp L 1 e bp 28 wM detail X (A 3) A
0
5 scale
10 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 3.3 0.13 A1 0.3 0.1 0.012 0.004 A2 3.0 2.8 0.12 0.11 A3 0.25 0.01 bp 0.42 0.30 c 0.22 0.14 D (1) 21.65 21.35 E (2) 11.1 11.0 e 0.75 HE 15.8 15.2 L 2.25 Lp 1.6 1.4 Q 1.45 1.30 v 0.2 w 0.1 y 0.1 Z (1) 0.90 0.55
0.017 0.0087 0.85 0.012 0.0055 0.84
0.44 0.62 0.0295 0.43 0.60
0.063 0.089 0.055
0.057 0.035 0.008 0.004 0.004 0.051 0.022
7 0o
o
Note 1. Plastic or metal protrusions of 0.3 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT190-1 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION
ISSUE DATE 96-04-02 97-08-11
1997 Apr 01
35
Philips Semiconductors
Product specification
LCD column driver for dot matrix graphic displays
PCF8579
LQFP64: plastic low profile quad flat package; 64 leads; body 10 x 10 x 1.4 mm
SOT314-2
c
y X A 48 49 33 32 ZE
e E HE wM bp 64 1 pin 1 index 16 ZD bp D HD wM B vM B vM A 17 detail X L Lp A A2 A1 (A 3)
e
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.60 A1 0.20 0.05 A2 1.45 1.35 A3 0.25 bp 0.27 0.17 c 0.18 0.12 D (1) 10.1 9.9 E (1) 10.1 9.9 e 0.5 HD HE L 1.0 Lp 0.75 0.45 v 0.2 w 0.12 y 0.1 Z D (1) Z E (1) 1.45 1.05 1.45 1.05 7 0o
o
12.15 12.15 11.85 11.85
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT314-2 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION
ISSUE DATE 95-12-19 97-08-01
1997 Apr 01
36
Philips Semiconductors
Product specification
LCD column driver for dot matrix graphic displays
18 SOLDERING 18.1 Introduction
PCF8579
* The footprint must be at an angle of 45 to the board direction and must incorporate solder thieves downstream and at the side corners. Even with these conditions, do not consider wave soldering LQFP packages LQFP48 (SOT313-2), LQFP64 (SOT314-2) or LQFP80 (SOT315-1). 18.3.2 VSO
There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "IC Package Databook" (order code 9398 652 90011). 18.2 Reflow soldering
Wave soldering techniques can be used for all VSO packages if the following conditions are observed: * A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. * The longitudinal axis of the package footprint must be parallel to the solder flow. * The package footprint must incorporate solder thieves at the downstream end. 18.3.3 METHOD (LQFP AND VSO)
Reflow soldering techniques are suitable for all LQFP and VSO packages. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 C. 18.3 18.3.1 Wave soldering LQFP
During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Maximum permissible solder temperature is 260 C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 C within 6 seconds. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 18.4 Repairing soldered joints
Wave soldering is not recommended for LQFP packages. This is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. If wave soldering cannot be avoided, the following conditions must be observed: * A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used.
Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
1997 Apr 01
37
Philips Semiconductors
Product specification
LCD column driver for dot matrix graphic displays
19 DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
PCF8579
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. 20 LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 21 PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011.
1997 Apr 01
38
Philips Semiconductors
Product specification
LCD column driver for dot matrix graphic displays
NOTES
PCF8579
1997 Apr 01
39
Philips Semiconductors - a worldwide company
Argentina: see South America Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. +61 2 9805 4455, Fax. +61 2 9805 4466 Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213, Tel. +43 1 60 101, Fax. +43 1 60 101 1210 Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6, 220050 MINSK, Tel. +375 172 200 733, Fax. +375 172 200 773 Belgium: see The Netherlands Brazil: see South America Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor, 51 James Bourchier Blvd., 1407 SOFIA, Tel. +359 2 689 211, Fax. +359 2 689 102 Canada: PHILIPS SEMICONDUCTORS/COMPONENTS, Tel. +1 800 234 7381 China/Hong Kong: 501 Hong Kong Industrial Technology Centre, 72 Tat Chee Avenue, Kowloon Tong, HONG KONG, Tel. +852 2319 7888, Fax. +852 2319 7700 Colombia: see South America Czech Republic: see Austria Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S, Tel. +45 32 88 2636, Fax. +45 31 57 1949 Finland: Sinikalliontie 3, FIN-02630 ESPOO, Tel. +358 9 615800, Fax. +358 9 61580/xxx France: 4 Rue du Port-aux-Vins, BP317, 92156 SURESNES Cedex, Tel. +33 1 40 99 6161, Fax. +33 1 40 99 6427 Germany: Hammerbrookstrae 69, D-20097 HAMBURG, Tel. +49 40 23 53 60, Fax. +49 40 23 536 300 Greece: No. 15, 25th March Street, GR 17778 TAVROS/ATHENS, Tel. +30 1 4894 339/239, Fax. +30 1 4814 240 Hungary: see Austria India: Philips INDIA Ltd, Shivsagar Estate, A Block, Dr. Annie Besant Rd. Worli, MUMBAI 400 018, Tel. +91 22 4938 541, Fax. +91 22 4938 722 Indonesia: see Singapore Ireland: Newstead, Clonskeagh, DUBLIN 14, Tel. +353 1 7640 000, Fax. +353 1 7640 200 Israel: RAPAC Electronics, 7 Kehilat Saloniki St, TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007 Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3, 20124 MILANO, Tel. +39 2 6752 2531, Fax. +39 2 6752 2557 Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108, Tel. +81 3 3740 5130, Fax. +81 3 3740 5077 Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL, Tel. +82 2 709 1412, Fax. +82 2 709 1415 Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR, Tel. +60 3 750 5214, Fax. +60 3 757 4880 Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905, Tel. +9-5 800 234 7381 Middle East: see Italy Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB, Tel. +31 40 27 82785, Fax. +31 40 27 88399 New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND, Tel. +64 9 849 4160, Fax. +64 9 849 7811 Norway: Box 1, Manglerud 0612, OSLO, Tel. +47 22 74 8000, Fax. +47 22 74 8341 Philippines: Philips Semiconductors Philippines Inc., 106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI, Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474 Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA, Tel. +48 22 612 2831, Fax. +48 22 612 2327 Portugal: see Spain Romania: see Italy Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW, Tel. +7 095 755 6918, Fax. +7 095 755 6919 Singapore: Lorong 1, Toa Payoh, SINGAPORE 1231, Tel. +65 350 2538, Fax. +65 251 6500 Slovakia: see Austria Slovenia: see Italy South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale, 2092 JOHANNESBURG, P.O. Box 7430 Johannesburg 2000, Tel. +27 11 470 5911, Fax. +27 11 470 5494 South America: Rua do Rocio 220, 5th floor, Suite 51, 04552-903 Sao Paulo, SAO PAULO - SP, Brazil, Tel. +55 11 821 2333, Fax. +55 11 829 1849 Spain: Balmes 22, 08007 BARCELONA, Tel. +34 3 301 6312, Fax. +34 3 301 4107 Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM, Tel. +46 8 632 2000, Fax. +46 8 632 2745 Switzerland: Allmendstrasse 140, CH-8027 ZURICH, Tel. +41 1 488 2686, Fax. +41 1 481 7730 Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1, TAIPEI, Taiwan Tel. +886 2 2134 2870, Fax. +886 2 2134 2874 Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd., 209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260, Tel. +66 2 745 4090, Fax. +66 2 398 0793 Turkey: Talatpasa Cad. No. 5, 80640 GULTEPE/ISTANBUL, Tel. +90 212 279 2770, Fax. +90 212 282 6707 Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7, 252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461 United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. +1 800 234 7381 Uruguay: see South America Vietnam: see Singapore Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD, Tel. +381 11 625 344, Fax.+381 11 635 777
For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 1997
Internet: http://www.semiconductors.philips.com
SCA53
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
417067/1200/03/pp40
Date of release: 1997 Apr 01
Document order number:
9397 750 01757

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